Hardware Verification by Universal Test Set Simulations, Sat and Bdds

In this paper we consider verification of combinational circuits by test vector simulations. The simulation-based verification under the presence of a fault model uses test pattern generation approach. We consider an implicit fault model that can possibly overcome incompleteness of explicit fault models considered so far. We show that the test vector generation can be enhanced by techniques used in formal verifications: SATand BDD-based solutions can be combined with the vector simulations. Our method can pass useful information between these disparate approaches. Tradeoffs between the three schemes are explored.